1. Field of the Invention
The present invention relates to a triac capable of operating in quadrants Q1 and Q4 and that can, in these quadrants, be turned on by a small gate current Igt, while having a low sensitivity to an unwanted turning-on by a voltage peak (dV/dt turning-on).
2. Discussion of the Related Art
FIG. 1 shows the equivalent diagram of a triac that comprises main terminals A1 and A2 and a gate terminal G referenced to terminal A2. By analogy with a thyristor, there is a tendency to call terminal A1 the anode and terminal A2 the cathode, but it should be noted that in a triac, terminal A1 is intended to be connected to a load, itself connected to a positive or negative A.C. supply voltage with respect to terminal A2. Considering that terminal A2 is grounded, the control quadrants of a triac are defined as follows:
first quadrant (Q1): A1 positive, G positive,
second quadrant (Q2): A1 positive, G negative,
third quadrant (Q3): A1 negative, G negative,
fourth quadrant (Q4): A1 negative, G positive.
FIGS. 2 and 3 respectively show a simplified cross-section view and a simplified top view of an example of a conventional triac. This triac is formed in a lightly-doped N-type substrate 1 surrounded with a heavily-doped P-type insulating wall. The rear surface of the structure essentially comprises a P-type layer 3. On the front surface side is formed a P-type well 5 in which are formed a main N-type region 6 and an auxiliary N-type region 7. On the rear surface side, in layer 3, is formed an N-type region 9 facing the P-type well, mainly in the regions unoccupied by main N-type region 6. The entire rear surface is coated with a metallization M1 intended to be connected to main terminal A1 of the triac. On the front surface side, a main metallization M2, in contact with well 5 and region 6, is intended to be connected to terminal A2 of the triac, generally connected to ground GND. There thus exists a thyristor Th1 formed of regions 3-1-5-6 that can be turned on in quadrants Q1 and Q2 and a thyristor Th2 formed of regions 5-1-3-9 that can be turned on in quadrants Q3 and Q4. Auxiliary N-type region 7 is coated with a metallization M3 intended to be connected to gate terminal G.
An N+-type channel stop ring substantially halfway between the limit of P well 5 and insulating wall 2 has further been shown in FIG. 2. Ring 11 is generally coated with a metallization 12 not connected to an external terminal. Similarly, the component periphery generally comprises a heavily-doped P-type ring 13, formed in insulating wall 2, coated with a metallization 14 unconnected to an external terminal. The portions of the upper silicon surface which are not in contact with a metallization are protected by an insulating layer 16, generally made of silicon oxide, and the entire upper surface, except for the metallization portions to be contacted, is coated with an insulating layer 17, for example, a PSG glass.
In the top view of FIG. 3, the internal portion of channel stop ring 11 has been shown. A portion of substrate 1 appears between the outside of P well 5 and ring 11. The limit of main N-type region 6 and the limit of auxiliary N-type region 7 have also been shown. On the one hand, the area in which metallization M2 is in contact with well 5 and region 6 and, on the other hand, the area in which metallization M3 is in contact on the one hand with the auxiliary gate region, on the other hand with a portion of well 5 (this contact between metallization M3 and a portion of P well 5 is not visible in the cross-section view of FIG. 2), have been shown with dotted lines. It should be reminded that the starting of a triac, which will not be described in detail herein, starts with the flowing of a current between the gate and the cathode along the resistive path designated as RGK in FIG. 3, which causes, after several intermediary steps, the turning-on of that of thyristors Th1 and Th2 which is properly biased.
It is known that such triacs can be relatively easily controlled in quadrants Q1, Q2, and Q3, but operate poorly or not at all in quadrant Q4. Thus, it is not possible to control the gate with a positive signal, whatever the biasing of the main triac terminals. This thus leads to systematically controlling the triacs in quadrants Q2 and Q3, that is, with a negative gate voltage with respect to ground, which makes control circuits more complex.
Further, because of integrated resistor RGK between the gate and the cathode, it is very difficult to obtain structures with a small gate-cathode control current further having good dynamic performance, especially as it relates to positive unwanted triggerings by abrupt voltage variations thereacross (dV/dt turning-on). Indeed, the smaller RGK, the higher the insensitivity to a dV/dt turning-on and, however, the higher the control currents must be. This is a disadvantage since it would be desired to be able to easily drive triacs with small currents to be able to, for example, control them directly with a microcontroller. On the other hand, the dV/dt strength is an important parameter to avoid triggerings by unwanted noise, especially in automobile applications.